The present invention generally relates to a thin film transistor (TFT) for use as a switching device in a liquid crystal display (LCD) and a method for fabrication and more particularly, relates to a TFT that is constructed with a multi-layer gate such that during the fabrication process, the top layer provides a reliable end point detection in the planarization of a polymeric material layer that the gate is embedded to ensure that no polymeric material is left on the top surface of the gate and a method for fabricating such TFT.
In recent years, large liquid crystal cells have been used in flat panel displays. The liquid crystal cells are normally constructed by two glass plates joined together with a layer of a liquid crystal material sandwiched inbetween. The glass substrates have conductive films coated thereon with at least one of the substrates being transparent. The substrates are connected to a source of power to change the orientation of the liquid crystal material. A possible source of power is a thin film transistor that is used to separately address areas of the liquid crystal cells at very fast rates. The TFT driven liquid crystal cells can be advantageously used in active matrix displays such as for television and computer monitors.
As the requirements for resolution of liquid crystal monitors increase, it becomes desirable to address a large number of separate areas of a liquid crystal cell, called pixels. For instance, in a modern display panel, more than 3,000,000 pixels may be present. At least the same number of transistors must therefore be formed on the glass plates so that each pixel can be separately addressed and left in the switched state while other pixels are addressed.
Thin film transistors are frequently made with either a polysilicon material or an amorphous silicon material. For TFT structures that are made of amorphous silicon material, a common structure is the inverted staggered type which can be back channel etched or tri-layered. The performance of a TFT and its manufacturing yield or throughput depend on the structure of the transistor. For instance, the inverted staggered back channel etched TFT can be fabricated with a minimum number of six masks, whereas other types of inverted staggered TFT require a minimum number of nine masks. The specification for a typical inverted staggered back channel etched TFT includes an amorphous silicon that has a thickness of 3,000 xc3x85, a gate insulator of silicon nitride or silicon oxide, a gate line of Mo/Ta, a signal line of Al/Mo and a storage capacitor. The requirement of a thick amorphous silicon layer in the TFT device is a drawback for achieving a high yield fabrication process since deposition of amorphous silicon is a slow process. A major benefit for the amorphous silicon TFT is its low leakage current which enables a pixel to maintain its voltage. On the other hand, an amorphous silicon TFT has the drawback of a low charge current (or on current) which requires an excessive amount of time for a pixel to be charged to its required voltage.
A second type of TFT is made by using a polysilicon material. Polysilicon is more frequently used for displays that are designed in a smaller size, for instance, up to three inch diagonal for a projection device. At such a small size, it is economical to fabricate the display device on a quartz substrate. Unfortunately, large area display devices cannot be normally made on quartz substrates. The desirable high performance of polysilicon can therefore be realized only if a low temperature process can be developed to enable the use of non-quartz substrates. For instance, in a more recently developed process, large area polysilicon TFT can be manufactured at processing temperatures of less than 600xc2x0 C. In the process, self-aligned transistors are made by depositing polysilicon and gate oxide followed by source/drain regions which are self-aligned to the gate electrode. The device is then completed with a thick oxide layer, an ITO layer and aluminum contacts.
Polysilicon TFTs have the advantage of a high charge current (or current) and the drawback of a high leakage current. It is difficult to maintain the voltage in a pixel until the next charge in a polysilicon TFT due to its high leakage current. Polysilicon also allows the formation of CMOS devices, which cannot be formed by amorphous silicon. For the fabrication of larger displays, a higher mobility may be achieved by reducing the trap density around the grain boundaries in a hydrogenation process.
FIG. 1 shows an enlarged, cross-sectional view of a conventional amorphous silicon TFT structure. Amorphous TFT 10 is built on a low cost glass substrate 12. On top of the glass substrate 12, a gate electrode 14 is first deposited of a refractory metal such as Cr, Al or Al alloy and then formed. A gate insulating layer 16 is normally formed in an oxidation process. For instance, a high density TaOx on a Ta gate can be formed to reduce defects such as pin holes and to improve yield. Another gate insulating layer 20 is then deposited of either silicon oxide or silicon nitride. An intrinsic amorphous silicon layer 22 is then deposited with a n+ doped amorphous silicon layer 24 deposited on top to improve its conductivity. Prior to the deposition of the doped amorphous silicon layer 24, an etch stop 26 is first deposited and formed to avoid damages to the amorphous silicon layer 22 in a subsequent etch process for a contact hole. The doped amorphous silicon layer 24 is formed by first depositing the amorphous silicon layer in a chemical vapor deposition process and then implanting ions in an ion implantation process. Boron ions are normally used to achieve n+ polarity. A drain region 30 and a source region 32 are then deposited and formed with a pixel electrode layer 34 of ITO (indium-tin-oxide) material deposited and formed on top. The drain region 30 and the source region 32 are normally deposited of a conductive metal layer. A suitable conductive metal may be a bilayer of Cr/Al. The structure is then passivated with a passivation layer 36.
A second conventional inverted staggered type TFT 40 is shown in FIG. 2. The TFT 40 is frequently called the back channel etched type inverted staggered TFT. A gate electrode 42 is first formed on a non-conducting glass substrate 38. The gate electrode 42 is connected to a gate line (not shown) laid out in the row direction. A dielectric material layer 44 of either silicon oxide or silicon nitride is used to insulate the gate electrode 42. After an amorphous silicon layer 46 and a contact layer 48 are sequentially deposited, patterned and etched, source electrode 50 and drain electrode 52 are formed to provide a channel 54 in-between the two electrodes, hence the name back channel etched TFT. The source electrode 50 of each TFT is connected to a transparent pixel electrode 56 independently formed in the area surrounded by the gate lines and the drain lines (not shown). A transparent passivation layer 58 of a material such as silicon nitride is deposited on the completed structure.
As shown in FIG. 2, the gate electrode 42 is frequently formed of chromium or other similar metals on the transparent glass substrate 38. The dielectric layer 44 of gate oxide or silicon nitride is formed to insulate the upper surface of the glass substrate 38 including the top surface of the gate electrode 42. A semi-conducting layer 46, which may be formed of amorphous silicon is stacked on the dielectric film 44 over the gate electrode 42. The drain electrode 52 and the source electrode 50 are formed on the semi-conducting film 46 and are separated from each other by a predetermined distance forming the channel section 54. The two electrodes each has a contact layer of 48 and a metal layer which are electrically connected to the semi-conducting layer 46. The transparent electrode 44 may be formed of ITO.
In modern TFT-LCD devices, it is desirable to have gate lines, or buslines that have lower electrical resistance so that the performance of the device can be improved. Various techniques have been used in the industry to achieve such purpose. One of the techniques is the use of a copper gate line for its lower electrical resistance. However, the fabrication process for a copper line is more difficult than for other metals that are usually used for the gate lines, i.e., aluminum. Another attempt to improving the gate line resistance is to make the lines wider. However, when the gate lines are designed with a larger width, more space is taken on the transparent substrate to reduce its light transparency which affects the total performance of the LCD. The approach of using a wider line is therefore not feasible. Still others have attempted to make the buslines thicker such that its resistance can be reduced. A thicker busline, even though does not occupy more substrate space in forming, is difficult to insulate by a dielectric layer which is subsequently deposited on top. Problems in step coverage and void formation occur when a silicon nitride layer is deposited over the top of a thick gate line. The insulation of a thick gate line, i.e., thicker than 3,000 xc3x85, therefore requires a new process which is not available in the present fabrication technology.
It is therefore an object of the present invention to provide a method for fabricating a TFT that has a multi-layer gate structure of large thickness that does not have the drawbacks or shortcomings of the conventional methods.
It is another object of the present invention to provide a method for fabricating a TFT that has a multi-layer gate structure of large thickness that can be effectively insulated by the deposition of more than one insulating layers.
It is a further object of the present invention to provide a method for fabricating a TFT that has a multi-layer gate structure of large thickness by insulating the gate structure with an insulative polymeric material layer in combination with a nitride dielectric layer.
It is another further object of the present invention to provide a method for fabricating a TFT that has a multi-layer gate structure of large thickness by coating the gate structure with a second metal layer on top which can be used for end point detection in a planarization process for the gate structure.
It is still another object of the present invention to provide a method for fabricating a TFT that has a multi-layer gate structure of large thickness wherein the gate structure has a thickness larger than 4,000 xc3x85.
It is yet another object of the present invention to provide a method for fabricating a TFT that has a multi-layer gate structure of large thickness wherein the gate structure has a thickness between about 4,000 xc3x85 and about 8,000 xc3x85.
It is still another further object of the present invention to provide a method for fabricating a TFT that has a multi-layer gate structure of large thickness wherein a metal gate is coated with a Mo layer before the deposition of an insulating polymeric layer.
It is yet another further object of the present invention to provide a method for fabricating a TFT that has a multi-layer gate structure of large thickness wherein a dry etching method is used incorporating an end point detection technique for planarizing an insulating polymeric material layer that embedded the gate structure.
In accordance with the present invention, a method for fabricating a TFT device which has a multi-layer gate structure of large thickness and the device fabricated are disclosed.
In a preferred embodiment, a method for fabricating a TFT that has a multi-layer gate structure can be carried out by the operating steps of first providing a non-electrical conductive substrate, forming a metal gate on the substrate, depositing and patterning a second metal layer overlying the metal gate, depositing an insulative polymeric material layer embedding the metal gate and the second metal layer, planarizing the insulative polymeric material layer until the second metal layer on a horizontal surface of the metal gate is completely exposed, and sequentially depositing a dielectric material layer, and intrinsic amorphous silicon layer, a n+ doped amorphous silicon layer and a third metal layer on top and forming a back channel exposing the n+ doped amorphous silicon.
The method for fabricating a TFT that has a multi-layer gate structure of large thickness may further include the step of depositing and forming an etch stop layer between the intrinsic amorphous silicon layer and the n+ doped amorphous silicon layer and forming a channel to expose the etch stop layer. The etch stop layer may be formed of silicon nitride. The second metal layer may be deposited of a metal selected from the group consisting of Mo, Cr, Ta and Ti. The method may further include the step of terminating the planarization step by an end point detection method when the second metal layer on top of a horizontal surface of the metal gate is completely exposed.
In the method, the third metal layer may be deposited of at least one metal selected from the group consisting of Mo, Cr and Al. The third metal layer may further be deposited of bi-layers of different metals. The dielectric material layer deposited on top of the second metal layer and the insulative polymeric material layer may be silicon nitride. The method may further include the step of forming the metal gate to a thickness of at least 4,000 xc3x85 for improved resistivity, or forming the metal gate to a thickness of between about 4,000 xc3x85 and about 10,000 xc3x85, and preferably between about 6,000 xc3x85 and about 8,000 xc3x85. The TFT formed may be a back channel-etched inverted staggered TFT, or a tri-layered inverted staggered TFT.
The method may further include the step of planarizing the insulative polymeric material layer by a reactive ion etching technique utilizing O2 and SF6 gases. The method may further include the step of patterning the second metal layer such that the entire metal gate is covered, the step of depositing the insulative polymeric material layer by a spin coating technique, and the step of forming a metal gate on the substrate as a busline for a TFT-LCD.
The present invention is further directed to a method for fabricating a TFT that has a multi-layer gate structure of large thickness by the operating steps of first providing a glass substrate that is substantially transparent, forming a metal gate on the substrate, depositing and patterning a Mo layer overlaying the metal gate, depositing an insulative polymeric material layer embedding the metal gate and the Mo layer, dry etching the insulative polymeric material layer and terminating the etching by an end point detection method when the Mo layer on a horizontal surface of the metal gate is completely exposed, and sequentially depositing a dielectric material layer, an intrinsic amorphous silicon layer, a n+ doped amorphous silicon layer and a third metal layer on top and forming a back channel exposing the n+ doped amorphous silicon.
The method for fabricating a TFT may further include the step of depositing and forming an etch-stop layer between the intrinsic amorphous silicon layer and the n+ doped amorphous silicon layer and forming a channel to expose the etch stop layer. The etch stop layer may be formed of silicon nitride. The third metal layer may be deposited of at least one metal selected from the group consisting of Mo, Cr and Al. The third metal layer may also be deposited of bi-layers of different metals. The dielectric material layer deposited on top of the Mo layer and the insulative polymeric material layer is silicon nitride. The method may further include the step of forming the metal gate to a thickness of between about 4,000 xc3x85 and about 10,000 xc3x85, and preferably between about 6,000 xc3x85 and about 8,000 xc3x85.
The method may further include the step of dry etching the insulative polymer material layer by a reactive ion etching technique utilizing etchant gases of O2 and SF6. The method may further include the step of patterning the Mo layer such that the entire metal gate is covered by Mo. The method may further include the step of depositing the insulative polymeric material layer by a spin coating technique and curing the layer between 250xcx9c350xc2x0 C. for at least xc2xd hour.
The present invention is further directed to a thin film transistor that has a multi-layer gate of large thickness which includes a glass substrate, a metal gate situated on the substrate having a planar top portion and sloped shoulder portions, a second metal layer substantially overlying the gate, an insulative polymeric material layer covering the substrate and the shoulder portions of the gate and is absent on the planar top portion of the gate, a dielectric layer embedding the planar top portion of the gate and the insulative polymeric material layer, and at least one amorphous silicon layer and a metal source/drain layer on top of the dielectric layer.
The TFT may further include a second metal layer which is formed of a metal selected from Mo, Cr, Ta and Ti. The metal gate may have a thickness between about 4,000 xc3x85 and about 10,000 xc3x85. The dielectric layer may be formed of silicon nitride. The at least one amorphous silicon layer includes an intrinsic amorphous silicon layer and an n+ doped amorphous silicon layer. The TFT may further include an etch-stop layer of a dielectric material situated between the at least one amorphous silicon layers.